1. Technical Field
The present invention relates to semiconductor fabrication, and more particularly to forming a defective p-n junction for backgated fully depleted silicon on insulator devices.
2. Description of the Related Art
In ultrathin fully depleted silicon on insulator (FDSOI) with thin buried oxide (BOX), pocket implants are placed underneath the BOX to adjust the threshold voltage Vt of the transistors. For example, with a BOX thickness of about 25 nm, changing the implant polarity shifts the threshold voltage by about 80 mV. To modulate the threshold voltage of the transistors during operation, a backgate voltage (backbias) is applied. To minimize the area penalty for connecting the backbias, it is applied to a well that is shared by several transistors. For those transistors that have a pocket implant, the backbias is applied to the BOX through a p-n junction that is located in series with the BOX. Since there is no DC current flowing through the p-n junction, in DC operation the backbias drops at the back interface of the BOX. However, during AC operation, there is a capacitive voltage divider formed by the MOS (metal-oxide-semiconductor) capacitor associated with the BOX and the depletion capacitor associated with the p-n junction between the well and pocket such that not all of the voltage drops across the BOX, causing the actual backbais to fluctuate.